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fixed some drc problems

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Squashed commit of the following:

commit fc0171f96f06824f930dc5825498fa5e5ecf1060
Author: daniel <github@dbauer.me>
Date:   Tue Jul 18 11:26:57 2023 +0200

    reversible slider

commit 837158be306a0aa2e166f52b0d32387ab34f280f
Author: daniel <github@dbauer.me>
Date:   Tue Jul 18 10:56:47 2023 +0200

    make hole footprints plated
This commit is contained in:
daniel
2023-07-18 14:55:41 +02:00
parent 1039b4d780
commit a66e1bbd06
5 changed files with 50435 additions and 49670 deletions
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279
pcb/pcbs/keyboard.kicad_pro
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@@ -34,9 +34,9 @@
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"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
"drill": 0.0,
"height": 2.6,
"width": 2.6
},
"silk_line_width": 0.12,
"silk_text_italic": false,
@@ -188,6 +188,217 @@
"cvpcb": {
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"erc": {
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"meta": {
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"rule_severities": {
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"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
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"libraries": {
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@@ -224,7 +435,7 @@
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Large",
"name": "large",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
@@ -408,11 +619,11 @@
"pattern": "ENCB_undef"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "GND_ENCA"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "ENCA_GND"
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{
@@ -424,7 +635,7 @@
"pattern": "ENCB"
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{
"netclass": "Large",
"netclass": "large",
"pattern": "GND"
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@@ -432,7 +643,7 @@
"pattern": "ENCA"
},
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"netclass": "Default",
"pattern": "RAW_P1"
},
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@@ -444,11 +655,11 @@
"pattern": "RST_GND"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "VCC_GND"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "P1_RAW"
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{
@@ -456,11 +667,11 @@
"pattern": "P0_GND"
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"netclass": "Default",
"pattern": "GND_RST"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "GND_VCC"
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{
@@ -476,7 +687,7 @@
"pattern": "CS"
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{
"netclass": "Large",
"netclass": "large",
"pattern": "RAW"
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{
@@ -484,15 +695,15 @@
"pattern": "RST"
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{
"netclass": "Large",
"netclass": "large",
"pattern": "VCC"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_VCC"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_GND_SCL"
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{
@@ -500,7 +711,7 @@
"pattern": "NN_SDA_CS"
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{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_SCL_GND"
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{
@@ -508,7 +719,7 @@
"pattern": "NN_CS_SDA"
},
{
"netclass": "Large",
"netclass": "large",
"pattern": "switch_from"
}
]
@@ -525,8 +736,38 @@
"page_layout_descr_file": ""
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"schematic": {
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"drawing": {
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"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
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"legacy_lib_dir": "",
"legacy_lib_list": []
"legacy_lib_list": [],
"meta": {
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"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
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"sheets": [],
"text_variables": {}