fixed some drc problems

Squashed commit of the following:

commit fc0171f96f06824f930dc5825498fa5e5ecf1060
Author: daniel <github@dbauer.me>
Date:   Tue Jul 18 11:26:57 2023 +0200

    reversible slider

commit 837158be306a0aa2e166f52b0d32387ab34f280f
Author: daniel <github@dbauer.me>
Date:   Tue Jul 18 10:56:47 2023 +0200

    make hole footprints plated
This commit is contained in:
daniel
2023-07-18 14:55:41 +02:00
parent 1039b4d780
commit a66e1bbd06
5 changed files with 50435 additions and 49670 deletions

View File

@@ -529,24 +529,15 @@ pcbs:
adjust:
shift: [20.50-2.5, -5.08]
rotate: -90
slider_f:
what: slider
slider:
what: slider_reversible
where: mcu
adjust:
shift: [-17.1, 0]
rotate: 90
params:
side: F
from: switch_from
to: RAW
slider_b:
what: slider
where: mcu
adjust:
shift: [-17.1, 0]
rotate: 90
params:
side: B
reverse: true
from: switch_from
to: RAW
battery:

View File

@@ -2,7 +2,7 @@ module.exports = {
params: {
class: "MP",
size: 4.0,
drill: 2.2
drill: 2.2
},
body: (p) => {
return `
@@ -12,7 +12,7 @@ module.exports = {
(effects (font (size 1 1) (thickness 0.15)))
)
(pad "" np_thru_hole circle (at 0 0) (size ${p.size} ${p.size}) (drill ${p.drill}) (layers *.Cu *.Mask) (tstamp 75b224f0-3010-4e8c-bf32-f95a770c96d9))
(pad "" thru_hole circle (at 0 0) (size ${p.size} ${p.size}) (drill ${p.drill}) (layers *.Cu *.Mask) (tstamp 75b224f0-3010-4e8c-bf32-f95a770c96d9))
)
`;
},

View File

@@ -0,0 +1,69 @@
module.exports = {
params: {
designator: 'T', // for Toggle
side: 'F',
reverse: false,
from: undefined,
to: undefined
},
body: p => {
const standard = `
(module E73:SPDT_C128955 (layer F.Cu) (tstamp 5BF2CC3C)
${p.at /* parametric position */}
${'' /* footprint reference */}
(fp_text reference "${p.ref}" (at 0 0) (layer F.SilkS) ${p.ref_hide} (effects (font (size 1.27 1.27) (thickness 0.15))))
(fp_text value "" (at 0 0) (layer F.SilkS) hide (effects (font (size 1.27 1.27) (thickness 0.15))))
${'' /* extra indicator for the slider */}
(fp_line (start -1.95 -3.85) (end 1.95 -3.85) (layer Dwgs.User) (width 0.15))
(fp_line (start 1.95 -3.85) (end 1.95 -1.35) (layer Dwgs.User) (width 0.15))
(fp_line (start -1.95 -1.35) (end -1.95 -3.85) (layer Dwgs.User) (width 0.15))
${'' /* bottom cutouts */}
(pad "" np_thru_hole circle (at 1.5 0) (size 1 1) (drill 0.9) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1.5 0) (size 1 1) (drill 0.9) (layers *.Cu *.Mask))
`
function pads(side, left, right) {
return `
${'' /* outline */}
(fp_line (start 1.95 -1.35) (end -1.95 -1.35) (layer ${side}.SilkS) (width 0.15))
(fp_line (start 0 -1.35) (end -3.3 -1.35) (layer ${side}.SilkS) (width 0.15))
(fp_line (start -3.3 -1.35) (end -3.3 1.5) (layer ${side}.SilkS) (width 0.15))
(fp_line (start -3.3 1.5) (end 3.3 1.5) (layer ${side}.SilkS) (width 0.15))
(fp_line (start 3.3 1.5) (end 3.3 -1.35) (layer ${side}.SilkS) (width 0.15))
(fp_line (start 0 -1.35) (end 3.3 -1.35) (layer ${side}.SilkS) (width 0.15))
${'' /* side mounts */}
(pad "" smd rect (at 3.7 -1.1 ${p.rot}) (size 0.9 0.9) (layers ${side}.Cu ${side}.Paste ${side}.Mask))
(pad "" smd rect (at 3.7 1.1 ${p.rot}) (size 0.9 0.9) (layers ${side}.Cu ${side}.Paste ${side}.Mask))
(pad "" smd rect (at -3.7 1.1 ${p.rot}) (size 0.9 0.9) (layers ${side}.Cu ${side}.Paste ${side}.Mask))
(pad "" smd rect (at -3.7 -1.1 ${p.rot}) (size 0.9 0.9) (layers ${side}.Cu ${side}.Paste ${side}.Mask))
${'' /* pins */}
(pad 1 smd rect (at ${right}2.25 2.075 ${p.rot}) (size 0.9 1.25) (layers ${side}.Cu ${side}.Paste ${side}.Mask) ${p.from.str})
(pad 2 smd rect (at ${left}0.75 2.075 ${p.rot}) (size 0.9 1.25) (layers ${side}.Cu ${side}.Paste ${side}.Mask) ${p.to.str})
(pad 3 smd rect (at ${left}2.25 2.075 ${p.rot}) (size 0.9 1.25) (layers ${side}.Cu ${side}.Paste ${side}.Mask))
`
}
const left = p.side == 'F' ? '-' : ''
const right = p.side == 'F' ? '' : '-'
if (p.reverse) {
return `
${standard}
${pads(p.side, left, right)}
${pads(p.side == 'F' ? 'B' : 'F', right, left)}
)`
} else {
return `
${standard}
${pads(p.side, left, right)}
)`
}
}
}

File diff suppressed because it is too large Load Diff

View File

@@ -34,9 +34,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.762,
"height": 1.524,
"width": 1.524
"drill": 0.0,
"height": 2.6,
"width": 2.6
},
"silk_line_width": 0.12,
"silk_text_italic": false,
@@ -188,6 +188,217 @@
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
@@ -224,7 +435,7 @@
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Large",
"name": "large",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.5,
@@ -408,11 +619,11 @@
"pattern": "ENCB_undef"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "GND_ENCA"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "ENCA_GND"
},
{
@@ -424,7 +635,7 @@
"pattern": "ENCB"
},
{
"netclass": "Large",
"netclass": "large",
"pattern": "GND"
},
{
@@ -432,7 +643,7 @@
"pattern": "ENCA"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "RAW_P1"
},
{
@@ -444,11 +655,11 @@
"pattern": "RST_GND"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "VCC_GND"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "P1_RAW"
},
{
@@ -456,11 +667,11 @@
"pattern": "P0_GND"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "GND_RST"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "GND_VCC"
},
{
@@ -476,7 +687,7 @@
"pattern": "CS"
},
{
"netclass": "Large",
"netclass": "large",
"pattern": "RAW"
},
{
@@ -484,15 +695,15 @@
"pattern": "RST"
},
{
"netclass": "Large",
"netclass": "large",
"pattern": "VCC"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_VCC"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_GND_SCL"
},
{
@@ -500,7 +711,7 @@
"pattern": "NN_SDA_CS"
},
{
"netclass": "Large",
"netclass": "Default",
"pattern": "NN_SCL_GND"
},
{
@@ -508,7 +719,7 @@
"pattern": "NN_CS_SDA"
},
{
"netclass": "Large",
"netclass": "large",
"pattern": "switch_from"
}
]
@@ -525,8 +736,38 @@
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": []
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [],
"text_variables": {}