fix ROL and RLA

src/main.rs

@@ -86,7 +86,7 @@ fn main() -> Result<(), Error> {
     let mut run = true;
     while let Some(event) = events.next(&mut window) {
         if let Some(_) = event.update_args() {
-            if cpu.regs.pc == 0xEE29  || cpu.regs.pc == 0xEE0E { run = false }
+            // if cpu.regs.pc == 0xEE29  || cpu.regs.pc == 0xEE0E { run = false }
             if run {
                 cpu.clock(&mut bus);
             }

src/nes/cpu.rs

@@ -896,7 +896,7 @@ impl CPU {
         };
         let shifted = (val << 1) as Byte | self.get_flag(CARRY);
         
-        self.set_flag(CARRY, (val & 0b1000000) == 0);
+        self.set_flag(CARRY, (val & 0b10000000) > 0);
         self.set_flag_nz(shifted);
 
         if *addr_mode == AddrMode::IMP {