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fix ROL and RLA

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This commit is contained in:
Daniel Bauer
2019-12-28 15:39:44 +01:00
parent 1bb0416522
commit e3dfc8b08f
2 changed files with 2 additions and 2 deletions
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2
src/main.rs
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@@ -86,7 +86,7 @@ fn main() -> Result<(), Error> {
let mut run = true; let mut run = true;
while let Some(event) = events.next(&mut window) { while let Some(event) = events.next(&mut window) {
if let Some(_) = event.update_args() { if let Some(_) = event.update_args() {
if cpu.regs.pc == 0xEE29 || cpu.regs.pc == 0xEE0E { run = false } // if cpu.regs.pc == 0xEE29 || cpu.regs.pc == 0xEE0E { run = false }
if run { if run {
cpu.clock(&mut bus); cpu.clock(&mut bus);
} }

2
src/nes/cpu.rs
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@@ -896,7 +896,7 @@ impl CPU {
}; };
let shifted = (val << 1) as Byte | self.get_flag(CARRY); let shifted = (val << 1) as Byte | self.get_flag(CARRY);
self.set_flag(CARRY, (val & 0b1000000) == 0); self.set_flag(CARRY, (val & 0b10000000) > 0);
self.set_flag_nz(shifted); self.set_flag_nz(shifted);
if *addr_mode == AddrMode::IMP { if *addr_mode == AddrMode::IMP {