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split bus and ppubus files

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This commit is contained in:
Daniel Bauer
2020-01-18 21:06:53 +01:00
parent 1e64f18f22
commit cc43894431
4 changed files with 108 additions and 99 deletions
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8
src/nes.rs
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@@ -4,16 +4,20 @@ pub use crate::nes::cartridge::Cartridge;
pub use crate::nes::ppu::PPU;
pub use crate::nes::cpu::CPU;
pub use crate::nes::types::*;
pub use crate::nes::memory::*;
pub use crate::nes::bus::*;
pub use crate::nes::ppubus::*;
#[allow(non_snake_case)]
pub mod cpu;
pub mod memory;
pub mod bus;
pub mod types;
pub mod disasm;
pub mod cartridge;
pub mod mappers;
pub mod ppu;
pub mod ppubus;
// The NES class connects all elements of the NES together. It acts
// as the mediator between the different components and hold the RAM

101
src/nes/bus.rs Normal file
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@@ -0,0 +1,101 @@
use crate::nes::ppu::PPU;
use crate::nes::ppubus::PPUBus;
use std::rc::Rc;
use core::cell::RefCell;
use crate::nes::cartridge::Cartridge;
use crate::nes::types::*;
pub const RAM_SIZE: usize = 0x0800;
pub const RAM_ADDR_RANGE: [Addr; 2] = [0x0000, 0x1fff];
pub const RAM_PHYS_RANGE: [Addr; 2] = [0x0000, 0x07ff];
pub const PPU_ADDR_RANGE: [Addr; 2] = [0x2000, 0x3fff];
pub const PPU_PHYS_RANGE: [Addr; 2] = [0x2000, 0x2007];
pub const CART_ADDR_RANGE: [Addr; 2] = [0x4020, 0xffff];
// NES memory: Contains data from RAM, cartridge...
pub struct Bus {
ram: [Byte; RAM_SIZE], // 2kb
cartridge: Option<Rc<RefCell<Cartridge>>>,
ppu: Rc<RefCell<PPU>>,
ppu_bus: Rc<RefCell<PPUBus>>,
}
impl Bus {
pub fn new(ppu: Rc<RefCell<PPU>>, ppu_bus: Rc<RefCell<PPUBus>>) -> Self {
Bus {
ram: [0; RAM_SIZE],
cartridge: None,
ppu: ppu,
ppu_bus: ppu_bus,
}
}
pub fn insert_cartridge(&mut self, c: Rc<RefCell<Cartridge>>) {
self.cartridge = Some(c);
}
}
pub trait Memory {
fn readb(&self, addr: Addr) -> Byte;
fn writeb(&mut self, addr: Addr, data: Byte);
fn readw(&self, addr: Addr) -> Word {
let lo = self.readb(addr);
let hi = self.readb(addr+1);
(hi as Word) << 8 | lo as Word
}
fn writew(&mut self, addr: Addr, data: Word) {
self.writeb(addr, data as Byte);
self.writeb(addr + 1, (data >> 8) as Byte);
}
}
impl Memory for Bus {
fn readb(&self, addr: Addr) -> Byte {
if let Some(cartridge) = &self.cartridge {
if CART_ADDR_RANGE[0] <= addr && addr <= CART_ADDR_RANGE[1] {
return cartridge.borrow().readb(addr)
}
}
if RAM_ADDR_RANGE[0] <= addr && addr <= RAM_ADDR_RANGE[1] {
// Ram is 3x mirrored after 0x07ff
return self.ram[(addr & RAM_PHYS_RANGE[1]) as usize]
}
if PPU_ADDR_RANGE[0] <= addr && addr <= PPU_ADDR_RANGE[1] {
let mut ppu = self.ppu.borrow_mut();
let ppu_bus = self.ppu_bus.borrow();
return ppu.readb(&*ppu_bus, addr & PPU_PHYS_RANGE[1]);
}
0x0000 // generic response
}
fn writeb(&mut self, addr: Addr, data: Byte) {
if let Some(cartridge) = &mut self.cartridge {
if CART_ADDR_RANGE[0] <= addr && addr <= CART_ADDR_RANGE[1] {
cartridge.borrow_mut().writeb(addr, data)
}
}
if RAM_ADDR_RANGE[0] <= addr && addr <= RAM_ADDR_RANGE[1] {
// Ram is 3x mirrored after 07ff
self.ram[(addr & RAM_PHYS_RANGE[1]) as usize] = data
}
if PPU_ADDR_RANGE[0] <= addr && addr <= PPU_ADDR_RANGE[1] {
let mut ppu = self.ppu.borrow_mut();
let mut ppu_bus = self.ppu_bus.borrow_mut();
ppu.writeb(&mut *ppu_bus, addr & PPU_PHYS_RANGE[1], data);
}
}
}
pub trait MemoryReader {
fn readb<T: Memory>(&self, mem: &T, addr: Addr) -> Byte {
mem.readb(addr)
}
fn readw<T: Memory>(&self, mem: &T, addr: Addr) -> Word {
mem.readw(addr)
}
fn writeb<T: Memory>(&mut self, mem: &mut T, addr: Addr, data: Byte) {
mem.writeb(addr, data)
}
}

2
src/nes/ppu.rs
View File

@@ -1,4 +1,4 @@
use crate::nes::memory::PPUMemory;
use crate::nes::ppubus::PPUMemory;
use crate::nes::types::*;
use image::{ImageBuffer, Rgba};
use palette::PALETTE;

96
src/nes/memory.rs → src/nes/ppubus.rs
View File

@@ -4,102 +4,6 @@ use core::cell::RefCell;
use crate::nes::cartridge::Cartridge;
use crate::nes::types::*;
pub const RAM_SIZE: usize = 0x0800;
pub const RAM_ADDR_RANGE: [Addr; 2] = [0x0000, 0x1fff];
pub const RAM_PHYS_RANGE: [Addr; 2] = [0x0000, 0x07ff];
pub const PPU_ADDR_RANGE: [Addr; 2] = [0x2000, 0x3fff];
pub const PPU_PHYS_RANGE: [Addr; 2] = [0x2000, 0x2007];
pub const CART_ADDR_RANGE: [Addr; 2] = [0x4020, 0xffff];
// NES memory: Contains data from RAM, cartridge...
pub struct Bus {
ram: [Byte; RAM_SIZE], // 2kb
cartridge: Option<Rc<RefCell<Cartridge>>>,
ppu: Rc<RefCell<PPU>>,
ppu_bus: Rc<RefCell<PPUBus>>,
}
impl Bus {
pub fn new(ppu: Rc<RefCell<PPU>>, ppu_bus: Rc<RefCell<PPUBus>>) -> Self {
Bus {
ram: [0; RAM_SIZE],
cartridge: None,
ppu: ppu,
ppu_bus: ppu_bus,
}
}
pub fn insert_cartridge(&mut self, c: Rc<RefCell<Cartridge>>) {
self.cartridge = Some(c);
}
}
pub trait Memory {
fn readb(&self, addr: Addr) -> Byte;
fn writeb(&mut self, addr: Addr, data: Byte);
fn readw(&self, addr: Addr) -> Word {
let lo = self.readb(addr);
let hi = self.readb(addr+1);
(hi as Word) << 8 | lo as Word
}
fn writew(&mut self, addr: Addr, data: Word) {
self.writeb(addr, data as Byte);
self.writeb(addr + 1, (data >> 8) as Byte);
}
}
impl Memory for Bus {
fn readb(&self, addr: Addr) -> Byte {
if let Some(cartridge) = &self.cartridge {
if CART_ADDR_RANGE[0] <= addr && addr <= CART_ADDR_RANGE[1] {
return cartridge.borrow().readb(addr)
}
}
if RAM_ADDR_RANGE[0] <= addr && addr <= RAM_ADDR_RANGE[1] {
// Ram is 3x mirrored after 0x07ff
return self.ram[(addr & RAM_PHYS_RANGE[1]) as usize]
}
if PPU_ADDR_RANGE[0] <= addr && addr <= PPU_ADDR_RANGE[1] {
let mut ppu = self.ppu.borrow_mut();
let ppu_bus = self.ppu_bus.borrow();
return ppu.readb(&*ppu_bus, addr & PPU_PHYS_RANGE[1]);
}
0x0000 // generic response
}
fn writeb(&mut self, addr: Addr, data: Byte) {
if let Some(cartridge) = &mut self.cartridge {
if CART_ADDR_RANGE[0] <= addr && addr <= CART_ADDR_RANGE[1] {
cartridge.borrow_mut().writeb(addr, data)
}
}
if RAM_ADDR_RANGE[0] <= addr && addr <= RAM_ADDR_RANGE[1] {
// Ram is 3x mirrored after 07ff
self.ram[(addr & RAM_PHYS_RANGE[1]) as usize] = data
}
if PPU_ADDR_RANGE[0] <= addr && addr <= PPU_ADDR_RANGE[1] {
let mut ppu = self.ppu.borrow_mut();
let mut ppu_bus = self.ppu_bus.borrow_mut();
ppu.writeb(&mut *ppu_bus, addr & PPU_PHYS_RANGE[1], data);
}
}
}
pub trait MemoryReader {
fn readb<T: Memory>(&self, mem: &T, addr: Addr) -> Byte {
mem.readb(addr)
}
fn readw<T: Memory>(&self, mem: &T, addr: Addr) -> Word {
mem.readw(addr)
}
fn writeb<T: Memory>(&mut self, mem: &mut T, addr: Addr, data: Byte) {
mem.writeb(addr, data)
}
}
pub const PATTERN_MEMORY_SIZE: usize = 4096;
pub const PATTERN_ADDR_RANGE: [Addr; 2] = [0x000, 0x1FFF];
pub const NAMETABLE_MEMORY_SIZE: usize = 1024;