From 903610b88d313e617a36fa1cb66d0bd4dfe47e3c Mon Sep 17 00:00:00 2001
From: Daniel Bauer <bauer@cbs.tu-darmstadt.de>
Date: Sat, 28 Dec 2019 11:54:19 +0100
Subject: [PATCH] DCP

---
 src/nes/cpu.rs              | 8 ++++++++
 src/nes/cpu/instructions.rs | 8 ++++++++
 2 files changed, 16 insertions(+)

diff --git a/src/nes/cpu.rs b/src/nes/cpu.rs
index ca9a037..e40cdfa 100644
--- a/src/nes/cpu.rs
+++ b/src/nes/cpu.rs
@@ -226,6 +226,7 @@ impl CPU {
             Operation::CMP => self.op_CMP(bus, value),
             Operation::CPX => self.op_CPX(bus, value),
             Operation::CPY => self.op_CPY(bus, value),
+            Operation::DCP => self.op_DCP(bus, value),
             Operation::DEC => self.op_DEC(bus, value),
             Operation::DEX => self.op_DEX(),
             Operation::DEY => self.op_DEY(),
@@ -640,6 +641,13 @@ impl CPU {
         true
     }
 
+    // Unofficial: DEC value, then CMP 
+    fn op_DCP<T: Memory>(&mut self, bus: &mut T, addr: Word) -> bool {
+        self.op_DEC(bus, addr);
+        self.op_CMP(bus, addr);
+        false
+    }
+
     // DEC - Decrement Memory
     // M,Z,N = M-1
     // Subtracts one from the value held at a specified memory location
diff --git a/src/nes/cpu/instructions.rs b/src/nes/cpu/instructions.rs
index c64ae3a..afb2a11 100644
--- a/src/nes/cpu/instructions.rs
+++ b/src/nes/cpu/instructions.rs
@@ -49,6 +49,7 @@ pub enum Operation {
     CMP,
     CPX,
     CPY,
+    DCP,
     DEC,
     DEX,
     DEY,
@@ -254,27 +255,34 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
     0xc0u8 => Instruction { opcode: 0xc0, addr_mode: AddrMode::IMM, operation: Operation::CPY, cycles: [2, 0] }, 
     0xc1u8 => Instruction { opcode: 0xc1, addr_mode: AddrMode::IZX, operation: Operation::CMP, cycles: [6, 0] }, 
     0xc2u8 => Instruction { opcode: 0xc2, addr_mode: AddrMode::IMM, operation: Operation::NOP, cycles: [2, 0] },
+    0xc3u8 => Instruction { opcode: 0xc3, addr_mode: AddrMode::IZX, operation: Operation::DCP, cycles: [7, 0] }, 
     0xc4u8 => Instruction { opcode: 0xc4, addr_mode: AddrMode::ZP0, operation: Operation::CPY, cycles: [3, 0] }, 
     0xc5u8 => Instruction { opcode: 0xc5, addr_mode: AddrMode::ZP0, operation: Operation::CMP, cycles: [3, 0] }, 
     0xc6u8 => Instruction { opcode: 0xc6, addr_mode: AddrMode::ZP0, operation: Operation::DEC, cycles: [5, 0] }, 
+    0xc7u8 => Instruction { opcode: 0xc7, addr_mode: AddrMode::ZP0, operation: Operation::DCP, cycles: [7, 0] }, 
     0xc8u8 => Instruction { opcode: 0xc8, addr_mode: AddrMode::IMP, operation: Operation::INY, cycles: [2, 0] }, 
     0xc9u8 => Instruction { opcode: 0xc9, addr_mode: AddrMode::IMM, operation: Operation::CMP, cycles: [2, 0] }, 
     0xcau8 => Instruction { opcode: 0xca, addr_mode: AddrMode::IMP, operation: Operation::DEX, cycles: [2, 0] }, 
     0xccu8 => Instruction { opcode: 0xcc, addr_mode: AddrMode::ABS, operation: Operation::CPY, cycles: [4, 0] }, 
     0xcdu8 => Instruction { opcode: 0xcd, addr_mode: AddrMode::ABS, operation: Operation::CMP, cycles: [4, 0] }, 
     0xceu8 => Instruction { opcode: 0xce, addr_mode: AddrMode::ABS, operation: Operation::DEC, cycles: [6, 0] }, 
+    0xcfu8 => Instruction { opcode: 0xcf, addr_mode: AddrMode::ABS, operation: Operation::DCP, cycles: [7, 0] }, 
     // 0xd0
     0xd0u8 => Instruction { opcode: 0xd0, addr_mode: AddrMode::REL, operation: Operation::BNE, cycles: [2, 0] }, 
+    0xd3u8 => Instruction { opcode: 0xd3, addr_mode: AddrMode::IZY, operation: Operation::DCP, cycles: [7, 0] }, 
     0xd1u8 => Instruction { opcode: 0xd1, addr_mode: AddrMode::IZY, operation: Operation::CMP, cycles: [5, 0] }, 
     0xd4u8 => Instruction { opcode: 0xd4, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
     0xd5u8 => Instruction { opcode: 0xd5, addr_mode: AddrMode::ZPX, operation: Operation::CMP, cycles: [4, 0] }, 
     0xd6u8 => Instruction { opcode: 0xd6, addr_mode: AddrMode::ZPX, operation: Operation::DEC, cycles: [6, 0] }, 
+    0xd7u8 => Instruction { opcode: 0xd7, addr_mode: AddrMode::ZPX, operation: Operation::DCP, cycles: [7, 0] }, 
     0xd8u8 => Instruction { opcode: 0xd8, addr_mode: AddrMode::IMP, operation: Operation::CLD, cycles: [2, 0] }, 
     0xd9u8 => Instruction { opcode: 0xd9, addr_mode: AddrMode::ABY, operation: Operation::CMP, cycles: [4, 0] }, 
     0xdau8 => Instruction { opcode: 0xda, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
+    0xdbu8 => Instruction { opcode: 0xdb, addr_mode: AddrMode::ABY, operation: Operation::DCP, cycles: [7, 0] }, 
     0xdcu8 => Instruction { opcode: 0xdc, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] },
     0xddu8 => Instruction { opcode: 0xdd, addr_mode: AddrMode::ABX, operation: Operation::CMP, cycles: [4, 0] }, 
     0xdeu8 => Instruction { opcode: 0xde, addr_mode: AddrMode::ABX, operation: Operation::DEC, cycles: [7, 0] }, 
+    0xdfu8 => Instruction { opcode: 0xdf, addr_mode: AddrMode::ABX, operation: Operation::DCP, cycles: [7, 0] }, 
     // 0xe0
     0xe0u8 => Instruction { opcode: 0xe0, addr_mode: AddrMode::IMM, operation: Operation::CPX, cycles: [2, 0] }, 
     0xe1u8 => Instruction { opcode: 0xe1, addr_mode: AddrMode::IZX, operation: Operation::SBC, cycles: [6, 0] },