disassembler
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@@ -1,8 +1,8 @@
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mod instructions;
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pub mod instructions;
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use instructions::{Instruction,Operation,AddrMode};
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use core::fmt::{Debug,Formatter,Result};
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use crate::nes::bus::Bus;
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use crate::nes::bus::*;
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use crate::nes::types::*;
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use log::{debug};
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@@ -52,8 +52,26 @@ pub struct CPU {
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cycles: u8, // number of clock clycles the CPU is ahead of global clock
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}
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// Default implementation to read/write from bus
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impl BusDevice for CPU { }
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// A cpu is clockable
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impl Clockable for CPU {
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fn clock<T: Bus>(&mut self, bus: &mut T) {
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if self.cycles == 0 {
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let opcode = self.readb_pc(bus);
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self.curr_op = opcode;
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let instruction = Instruction::decode_op(opcode).unwrap(); // TODO error handling
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self.cycles = self.run_instruction(bus, instruction);
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}
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debug!("{:?}", self);
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self.cycles -= 1;
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}
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}
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impl CPU {
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pub fn new() -> CPU {
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pub fn new() -> Self {
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CPU {
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regs: Registers::new(),
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cycles: 0,
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@@ -91,18 +109,6 @@ impl CPU {
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return self.cycles > 0;
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}
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fn readb<T: Bus>(&self, bus: &T, addr: Addr) -> Byte {
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bus.readb(addr)
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}
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fn readw<T: Bus>(&self, bus: &T, addr: Addr) -> Word {
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bus.readw(addr)
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}
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fn writeb<T: Bus>(&mut self, bus: &mut T, addr: Addr, data: Byte) {
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bus.writeb(addr, data)
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}
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// read the next opcode and increment pc
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fn readb_pc<T: Bus>(&mut self, bus: &T) -> Byte {
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let val = self.readb(bus, self.regs.pc);
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@@ -135,19 +141,6 @@ impl CPU {
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}
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}
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pub fn clock<T: Bus>(&mut self, bus: &mut T) {
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if self.cycles == 0 {
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let opcode = self.readb_pc(bus);
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self.curr_op = opcode;
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let instruction = Instruction::decode_op(opcode).unwrap(); // TODO error handling
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self.cycles = self.run_instruction(bus, instruction);
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}
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debug!("{:?}", self);
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self.cycles -= 1;
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}
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fn run_instruction<T: Bus>(&mut self, bus: &mut T, i: &Instruction) -> u8 {
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let (value, page_cross) = match &i.addr_mode {
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AddrMode::IMP => self.am_IMP(bus),
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