From 1bb04165228fa1b9dd8fc578665fb9431d88adfd Mon Sep 17 00:00:00 2001
From: Daniel Bauer <bauer@cbs.tu-darmstadt.de>
Date: Sat, 28 Dec 2019 15:37:13 +0100
Subject: [PATCH] fix ASL, impl SLO

---
 src/main.rs    |  2 +-
 src/nes/cpu.rs | 35 ++++++++++++++++++++++++++++++-----
 2 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 79acb05..fa1b83a 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -86,7 +86,7 @@ fn main() -> Result<(), Error> {
     let mut run = true;
     while let Some(event) = events.next(&mut window) {
         if let Some(_) = event.update_args() {
-            // if cpu.regs.pc == 0xD031 || cpu.regs.pc == 0xD01A  { run = false }
+            if cpu.regs.pc == 0xEE29  || cpu.regs.pc == 0xEE0E { run = false }
             if run {
                 cpu.clock(&mut bus);
             }
diff --git a/src/nes/cpu.rs b/src/nes/cpu.rs
index 790117c..155b36a 100644
--- a/src/nes/cpu.rs
+++ b/src/nes/cpu.rs
@@ -218,7 +218,7 @@ impl CPU {
             Operation::AND => self.op_AND(bus, value),
             Operation::ASL => self.op_ASL(bus, value),
             Operation::BCC => self.op_BCC(bus, value),
-            Operation::BCS => self.op_BCS(bus, value),
+            Operation::BCS => self.op_BCS(value),
             Operation::BEQ => self.op_BEQ(bus, value),
             Operation::BIT => self.op_BIT(bus, value),
             Operation::BMI => self.op_BMI(bus, value),
@@ -258,7 +258,9 @@ impl CPU {
             Operation::PLA => self.op_PLA(bus),
             Operation::ROL => self.op_ROL(bus, value),
             Operation::PLP => self.op_PLP(bus),
+            Operation::RLA => self.op_RLA(bus, value),
             Operation::ROR => self.op_ROR(bus, value),
+            Operation::RRA => self.op_RRA(bus, value),
             Operation::RTI => self.op_RTI(bus),
             Operation::RTS => self.op_RTS(bus),
             Operation::SAX => self.op_SAX(bus, value),
@@ -267,6 +269,7 @@ impl CPU {
             Operation::SED => self.op_SED(),
             Operation::SEI => self.op_SEI(),
             Operation::SLO => self.op_SLO(bus, value),
+            Operation::SRE => self.op_SRE(bus, value),
             Operation::STA => self.op_STA(bus, value),
             Operation::STX => self.op_STX(bus, value),
             Operation::STY => self.op_STY(bus, value),
@@ -471,7 +474,7 @@ impl CPU {
             self.readb(bus, addr)
         };
         let shifted = (val << 1) as Byte;
-        self.set_flag(CARRY, (val & 0b1000000) == 0);
+        self.set_flag(CARRY, (val & 0b10000000) > 0);
 
         if *addr_mode == AddrMode::IMP {
             self.regs.a = shifted;
@@ -497,7 +500,7 @@ impl CPU {
         // BCC - Branch if Carry Set
     // If the carry flag is set then add the relative displacement to the
     // program counter to cause a branch to a new location.
-    fn op_BCS<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
+    fn op_BCS(&mut self, addr: Addr) -> bool {
         if self.get_flag(CARRY) == 1 {
             self.jump(addr);
         }
@@ -840,7 +843,7 @@ impl CPU {
     // An inclusive OR is performed, bit by bit, on the accumulator contents
     // using the contents of a byte of memory.
     fn op_ORA<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
-        self.regs.a |= self.readb(bus, addr);
+        self.regs.a = self.regs.a | self.readb(bus, addr);
         self.set_flag_nz(self.regs.a);
         true
     }
@@ -904,6 +907,21 @@ impl CPU {
         false
     }
 
+    // Unofficial: ROL and then AND
+    fn op_RLA<T: Memory>(&mut self, bus: &mut T, addr: Addr) -> bool {
+        self.op_ROL(bus, addr);
+        self.op_AND(bus, addr);
+
+        false
+    }
+
+    // Unofficial: Performs ROR + ADC
+    fn op_RRA<T: Memory>(&mut self, bus: &mut T, addr: Addr) -> bool {
+        self.op_ROR(bus, addr);
+        self.op_ADC(bus, addr);
+        false
+    }
+
     // ROR - Rotate Right
     // Move each of the bits in either A or M one place to the right. Bit 7 is
     // filled with the current value of the carry flag whilst the old bit 0
@@ -1013,13 +1031,20 @@ impl CPU {
         false
     }
 
-    // Unofficial opcode: ASL then ORA
+    // Unofficial: ASL + ORA
     fn op_SLO<T: Memory>(&mut self, bus: &mut T, addr: Word) -> bool {
         self.op_ASL(bus, addr);
         self.op_ORA(bus, addr);
         false
     }
 
+    // Unofficial: LSR + EOR
+    fn op_SRE<T: Memory>(&mut self, bus: &mut T, addr: Word) -> bool {
+        self.op_LSR(bus, addr);
+        self.op_EOR(bus, addr);
+        false
+    }
+
     // Push A reg to memory
     fn op_STA<T: Memory>(&mut self, bus: &mut T, addr: Word) -> bool {
         self.writeb(bus, addr, self.regs.a);