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work on cycles accuracy

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This commit is contained in:
Daniel Bauer
2019-12-28 20:32:26 +01:00
parent e5ccd50b9d
commit 04ba4d8da1
3 changed files with 68 additions and 47 deletions
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2
src/main.rs
View File

@@ -86,7 +86,7 @@ fn main() -> Result<(), Error> {
let mut run = true; let mut run = true;
while let Some(event) = events.next(&mut window) { while let Some(event) = events.next(&mut window) {
if let Some(_) = event.update_args() { if let Some(_) = event.update_args() {
if cpu.regs.pc == 0xC6A2 { run = false } // if cpu.regs.pc == 0xC6A2 { run = false }
if run { if run {
cpu.clock(&mut bus); cpu.clock(&mut bus);
} }

31
src/nes/cpu.rs
View File

@@ -39,7 +39,7 @@ impl Debug for Registers {
pub const STACK_BASE_ADDR: Addr = 0x0100; pub const STACK_BASE_ADDR: Addr = 0x0100;
pub const LO: Addr = 0x00FF; pub const LO: Addr = 0x00FF;
pub const HI: Addr = 0xFFFF; pub const HI: Addr = 0xFF00;
pub const CARRY: Byte = 1 << 0; // 0000 0001 0x01 pub const CARRY: Byte = 1 << 0; // 0000 0001 0x01
pub const ZERO: Byte = 1 << 1; // 0000 0010 0x02 pub const ZERO: Byte = 1 << 1; // 0000 0010 0x02
@@ -73,10 +73,11 @@ impl Clockable for CPU {
let opcode = self.readb_pc(bus); let opcode = self.readb_pc(bus);
self.curr_op = opcode; self.curr_op = opcode;
let instruction = Instruction::decode_op(opcode); let instruction = Instruction::decode_op(opcode);
info!("{:#06X} {:02X} {} A:{:02X} X:{:02X} Y:{:02X} P:{:02X} SP:{:02X} CYC:{}", info!("{:#06X} {:02X} {} A:{:02X} X:{:02X} Y:{:02X} P:{:02X} SP:{:02X} CYC:{}",
self.regs.pc-1, opcode, instruction.operation, self.regs.pc-1, opcode, instruction.operation,
self.regs.a, self.regs.x, self.regs.y, self.regs.flags, self.regs.sp, self.cycles); self.regs.a, self.regs.x, self.regs.y, self.regs.flags, self.regs.sp, self.cycles);
self.cycles_ahead = self.run_instruction(bus, instruction); self.cycles_ahead += self.run_instruction(bus, instruction);
} }
self.cycles_ahead -= 1; self.cycles_ahead -= 1;
self.cycles += 1 self.cycles += 1
@@ -362,7 +363,8 @@ impl CPU {
} else { } else {
base_addr + rel_addr - 256 base_addr + rel_addr - 256
}; };
(addr, false)
(addr, addr & HI != base_addr & HI)
} }
// the next 16 bits are an address. This address stores the real address // the next 16 bits are an address. This address stores the real address
@@ -409,7 +411,7 @@ impl CPU {
let addr = (hi as Word) << 8 | lo as Word; let addr = (hi as Word) << 8 | lo as Word;
let addr = addr.wrapping_add(self.regs.y as Word); let addr = addr.wrapping_add(self.regs.y as Word);
if addr & HI != (hi as Word) << 8 { if addr & HI != (hi as Word) << 8 & HI {
(addr, true) (addr, true)
} else { } else {
(addr, false) (addr, false)
@@ -493,6 +495,8 @@ impl CPU {
fn op_BCC<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool { fn op_BCC<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
if self.get_flag(CARRY) == 0 { if self.get_flag(CARRY) == 0 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -503,6 +507,8 @@ impl CPU {
fn op_BCS(&mut self, addr: Addr) -> bool { fn op_BCS(&mut self, addr: Addr) -> bool {
if self.get_flag(CARRY) == 1 { if self.get_flag(CARRY) == 1 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -513,6 +519,8 @@ impl CPU {
fn op_BEQ<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool { fn op_BEQ<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
if self.get_flag(ZERO) == 1 { if self.get_flag(ZERO) == 1 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -535,6 +543,8 @@ impl CPU {
fn op_BMI<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool { fn op_BMI<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
if self.get_flag(NEGATIVE) == 1 { if self.get_flag(NEGATIVE) == 1 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -545,6 +555,8 @@ impl CPU {
fn op_BNE(&mut self, addr: Addr) -> bool { fn op_BNE(&mut self, addr: Addr) -> bool {
if self.get_flag(ZERO) == 0 { if self.get_flag(ZERO) == 0 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -555,6 +567,8 @@ impl CPU {
fn op_BPL<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool { fn op_BPL<T: Memory>(&mut self, bus: &T, addr: Addr) -> bool {
if self.get_flag(NEGATIVE) == 0 { if self.get_flag(NEGATIVE) == 0 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -588,6 +602,8 @@ impl CPU {
fn op_BVC(&mut self, addr: Addr) -> bool { fn op_BVC(&mut self, addr: Addr) -> bool {
if self.get_flag(OVERFLOW) == 0 { if self.get_flag(OVERFLOW) == 0 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -598,6 +614,8 @@ impl CPU {
fn op_BVS(&mut self, addr: Addr) -> bool { fn op_BVS(&mut self, addr: Addr) -> bool {
if self.get_flag(OVERFLOW) == 1 { if self.get_flag(OVERFLOW) == 1 {
self.jump(addr); self.jump(addr);
self.cycles_ahead += 1;
return true
} }
false false
} }
@@ -835,7 +853,10 @@ impl CPU {
// does nothing // does nothing
fn op_NOP(&mut self) -> bool { fn op_NOP(&mut self) -> bool {
false match Instruction::decode_op(self.curr_op).addr_mode {
AddrMode::ABX => true,
_ => false,
}
} }
// ORA - Logical Inclusive OR // ORA - Logical Inclusive OR

80
src/nes/cpu/instructions.rs
View File

@@ -131,8 +131,8 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x0eu8 => Instruction { opcode: 0x0e, addr_mode: AddrMode::ABS, operation: Operation::ASL, cycles: [6, 0] }, 0x0eu8 => Instruction { opcode: 0x0e, addr_mode: AddrMode::ABS, operation: Operation::ASL, cycles: [6, 0] },
0x0fu8 => Instruction { opcode: 0x0f, addr_mode: AddrMode::ABS, operation: Operation::SLO, cycles: [6, 0] }, 0x0fu8 => Instruction { opcode: 0x0f, addr_mode: AddrMode::ABS, operation: Operation::SLO, cycles: [6, 0] },
// 0x10 // 0x10
0x10u8 => Instruction { opcode: 0x10, addr_mode: AddrMode::REL, operation: Operation::BPL, cycles: [2, 0] }, 0x10u8 => Instruction { opcode: 0x10, addr_mode: AddrMode::REL, operation: Operation::BPL, cycles: [2, 1] },
0x11u8 => Instruction { opcode: 0x11, addr_mode: AddrMode::IZY, operation: Operation::ORA, cycles: [5, 0] }, 0x11u8 => Instruction { opcode: 0x11, addr_mode: AddrMode::IZY, operation: Operation::ORA, cycles: [5, 1] },
0x12u8 => Instruction { opcode: 0x12, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0x12u8 => Instruction { opcode: 0x12, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0x13u8 => Instruction { opcode: 0x13, addr_mode: AddrMode::IZY, operation: Operation::SLO, cycles: [8, 0] }, 0x13u8 => Instruction { opcode: 0x13, addr_mode: AddrMode::IZY, operation: Operation::SLO, cycles: [8, 0] },
0x14u8 => Instruction { opcode: 0x14, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0x14u8 => Instruction { opcode: 0x14, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
@@ -140,11 +140,11 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x16u8 => Instruction { opcode: 0x16, addr_mode: AddrMode::ZPX, operation: Operation::ASL, cycles: [6, 0] }, 0x16u8 => Instruction { opcode: 0x16, addr_mode: AddrMode::ZPX, operation: Operation::ASL, cycles: [6, 0] },
0x17u8 => Instruction { opcode: 0x17, addr_mode: AddrMode::ZPX, operation: Operation::SLO, cycles: [6, 0] }, 0x17u8 => Instruction { opcode: 0x17, addr_mode: AddrMode::ZPX, operation: Operation::SLO, cycles: [6, 0] },
0x18u8 => Instruction { opcode: 0x18, addr_mode: AddrMode::IMP, operation: Operation::CLC, cycles: [2, 0] }, 0x18u8 => Instruction { opcode: 0x18, addr_mode: AddrMode::IMP, operation: Operation::CLC, cycles: [2, 0] },
0x19u8 => Instruction { opcode: 0x19, addr_mode: AddrMode::ABY, operation: Operation::ORA, cycles: [4, 0] }, 0x19u8 => Instruction { opcode: 0x19, addr_mode: AddrMode::ABY, operation: Operation::ORA, cycles: [4, 1] },
0x1au8 => Instruction { opcode: 0x1a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0x1au8 => Instruction { opcode: 0x1a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0x1bu8 => Instruction { opcode: 0x1b, addr_mode: AddrMode::ABY, operation: Operation::SLO, cycles: [7, 0] }, 0x1bu8 => Instruction { opcode: 0x1b, addr_mode: AddrMode::ABY, operation: Operation::SLO, cycles: [7, 0] },
0x1cu8 => Instruction { opcode: 0x1c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0x1cu8 => Instruction { opcode: 0x1c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0x1du8 => Instruction { opcode: 0x1d, addr_mode: AddrMode::ABX, operation: Operation::ORA, cycles: [4, 0] }, 0x1du8 => Instruction { opcode: 0x1d, addr_mode: AddrMode::ABX, operation: Operation::ORA, cycles: [4, 1] },
0x1eu8 => Instruction { opcode: 0x1e, addr_mode: AddrMode::ABX, operation: Operation::ASL, cycles: [7, 0] }, 0x1eu8 => Instruction { opcode: 0x1e, addr_mode: AddrMode::ABX, operation: Operation::ASL, cycles: [7, 0] },
0x1fu8 => Instruction { opcode: 0x1f, addr_mode: AddrMode::ABX, operation: Operation::SLO, cycles: [7, 0] }, 0x1fu8 => Instruction { opcode: 0x1f, addr_mode: AddrMode::ABX, operation: Operation::SLO, cycles: [7, 0] },
// 0x20 // 0x20
@@ -165,8 +165,8 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x2eu8 => Instruction { opcode: 0x2e, addr_mode: AddrMode::ABS, operation: Operation::ROL, cycles: [6, 0] }, 0x2eu8 => Instruction { opcode: 0x2e, addr_mode: AddrMode::ABS, operation: Operation::ROL, cycles: [6, 0] },
0x2fu8 => Instruction { opcode: 0x2f, addr_mode: AddrMode::ABS, operation: Operation::RLA, cycles: [6, 0] }, 0x2fu8 => Instruction { opcode: 0x2f, addr_mode: AddrMode::ABS, operation: Operation::RLA, cycles: [6, 0] },
// 0x30 // 0x30
0x30u8 => Instruction { opcode: 0x30, addr_mode: AddrMode::REL, operation: Operation::BMI, cycles: [2, 0] }, 0x30u8 => Instruction { opcode: 0x30, addr_mode: AddrMode::REL, operation: Operation::BMI, cycles: [2, 1] },
0x31u8 => Instruction { opcode: 0x31, addr_mode: AddrMode::IZY, operation: Operation::AND, cycles: [5, 0] }, 0x31u8 => Instruction { opcode: 0x31, addr_mode: AddrMode::IZY, operation: Operation::AND, cycles: [5, 1] },
0x32u8 => Instruction { opcode: 0x32, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0x32u8 => Instruction { opcode: 0x32, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0x33u8 => Instruction { opcode: 0x33, addr_mode: AddrMode::IZY, operation: Operation::RLA, cycles: [8, 0] }, 0x33u8 => Instruction { opcode: 0x33, addr_mode: AddrMode::IZY, operation: Operation::RLA, cycles: [8, 0] },
0x34u8 => Instruction { opcode: 0x34, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0x34u8 => Instruction { opcode: 0x34, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
@@ -174,11 +174,11 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x36u8 => Instruction { opcode: 0x36, addr_mode: AddrMode::ZPX, operation: Operation::ROL, cycles: [6, 0] }, 0x36u8 => Instruction { opcode: 0x36, addr_mode: AddrMode::ZPX, operation: Operation::ROL, cycles: [6, 0] },
0x37u8 => Instruction { opcode: 0x37, addr_mode: AddrMode::ZPX, operation: Operation::RLA, cycles: [6, 0] }, 0x37u8 => Instruction { opcode: 0x37, addr_mode: AddrMode::ZPX, operation: Operation::RLA, cycles: [6, 0] },
0x38u8 => Instruction { opcode: 0x38, addr_mode: AddrMode::IMP, operation: Operation::SEC, cycles: [2, 0] }, 0x38u8 => Instruction { opcode: 0x38, addr_mode: AddrMode::IMP, operation: Operation::SEC, cycles: [2, 0] },
0x39u8 => Instruction { opcode: 0x39, addr_mode: AddrMode::ABY, operation: Operation::AND, cycles: [4, 0] }, 0x39u8 => Instruction { opcode: 0x39, addr_mode: AddrMode::ABY, operation: Operation::AND, cycles: [4, 1] },
0x3au8 => Instruction { opcode: 0x3a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0x3au8 => Instruction { opcode: 0x3a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0x3bu8 => Instruction { opcode: 0x3b, addr_mode: AddrMode::ABY, operation: Operation::RLA, cycles: [7, 0] }, 0x3bu8 => Instruction { opcode: 0x3b, addr_mode: AddrMode::ABY, operation: Operation::RLA, cycles: [7, 0] },
0x3cu8 => Instruction { opcode: 0x3c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0x3cu8 => Instruction { opcode: 0x3c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0x3du8 => Instruction { opcode: 0x3d, addr_mode: AddrMode::ABX, operation: Operation::AND, cycles: [4, 0] }, 0x3du8 => Instruction { opcode: 0x3d, addr_mode: AddrMode::ABX, operation: Operation::AND, cycles: [4, 1] },
0x3eu8 => Instruction { opcode: 0x3e, addr_mode: AddrMode::ABX, operation: Operation::ROL, cycles: [7, 0] }, 0x3eu8 => Instruction { opcode: 0x3e, addr_mode: AddrMode::ABX, operation: Operation::ROL, cycles: [7, 0] },
0x3fu8 => Instruction { opcode: 0x3f, addr_mode: AddrMode::ABX, operation: Operation::RLA, cycles: [7, 0] }, 0x3fu8 => Instruction { opcode: 0x3f, addr_mode: AddrMode::ABX, operation: Operation::RLA, cycles: [7, 0] },
// 0x40 // 0x40
@@ -199,8 +199,8 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x4eu8 => Instruction { opcode: 0x4e, addr_mode: AddrMode::ABS, operation: Operation::LSR, cycles: [6, 0] }, 0x4eu8 => Instruction { opcode: 0x4e, addr_mode: AddrMode::ABS, operation: Operation::LSR, cycles: [6, 0] },
0x4fu8 => Instruction { opcode: 0x4f, addr_mode: AddrMode::ABS, operation: Operation::SRE, cycles: [6, 0] }, 0x4fu8 => Instruction { opcode: 0x4f, addr_mode: AddrMode::ABS, operation: Operation::SRE, cycles: [6, 0] },
// 0x50 // 0x50
0x50u8 => Instruction { opcode: 0x50, addr_mode: AddrMode::REL, operation: Operation::BVC, cycles: [2, 0] }, 0x50u8 => Instruction { opcode: 0x50, addr_mode: AddrMode::REL, operation: Operation::BVC, cycles: [2, 1] },
0x51u8 => Instruction { opcode: 0x51, addr_mode: AddrMode::IZY, operation: Operation::EOR, cycles: [5, 0] }, 0x51u8 => Instruction { opcode: 0x51, addr_mode: AddrMode::IZY, operation: Operation::EOR, cycles: [5, 1] },
0x52u8 => Instruction { opcode: 0x52, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0x52u8 => Instruction { opcode: 0x52, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0x53u8 => Instruction { opcode: 0x53, addr_mode: AddrMode::IZY, operation: Operation::SRE, cycles: [8, 0] }, 0x53u8 => Instruction { opcode: 0x53, addr_mode: AddrMode::IZY, operation: Operation::SRE, cycles: [8, 0] },
0x54u8 => Instruction { opcode: 0x54, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0x54u8 => Instruction { opcode: 0x54, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
@@ -208,11 +208,11 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x56u8 => Instruction { opcode: 0x56, addr_mode: AddrMode::ZPX, operation: Operation::LSR, cycles: [6, 0] }, 0x56u8 => Instruction { opcode: 0x56, addr_mode: AddrMode::ZPX, operation: Operation::LSR, cycles: [6, 0] },
0x57u8 => Instruction { opcode: 0x57, addr_mode: AddrMode::ZPX, operation: Operation::SRE, cycles: [6, 0] }, 0x57u8 => Instruction { opcode: 0x57, addr_mode: AddrMode::ZPX, operation: Operation::SRE, cycles: [6, 0] },
0x58u8 => Instruction { opcode: 0x58, addr_mode: AddrMode::IMP, operation: Operation::CLI, cycles: [2, 0] }, 0x58u8 => Instruction { opcode: 0x58, addr_mode: AddrMode::IMP, operation: Operation::CLI, cycles: [2, 0] },
0x59u8 => Instruction { opcode: 0x59, addr_mode: AddrMode::ABY, operation: Operation::EOR, cycles: [4, 0] }, 0x59u8 => Instruction { opcode: 0x59, addr_mode: AddrMode::ABY, operation: Operation::EOR, cycles: [4, 1] },
0x5au8 => Instruction { opcode: 0x5a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0x5au8 => Instruction { opcode: 0x5a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0x5bu8 => Instruction { opcode: 0x5b, addr_mode: AddrMode::ABY, operation: Operation::SRE, cycles: [7, 0] }, 0x5bu8 => Instruction { opcode: 0x5b, addr_mode: AddrMode::ABY, operation: Operation::SRE, cycles: [7, 0] },
0x5cu8 => Instruction { opcode: 0x5c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0x5cu8 => Instruction { opcode: 0x5c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0x5du8 => Instruction { opcode: 0x5d, addr_mode: AddrMode::ABX, operation: Operation::EOR, cycles: [4, 0] }, 0x5du8 => Instruction { opcode: 0x5d, addr_mode: AddrMode::ABX, operation: Operation::EOR, cycles: [4, 1] },
0x5eu8 => Instruction { opcode: 0x5e, addr_mode: AddrMode::ABX, operation: Operation::LSR, cycles: [7, 0] }, 0x5eu8 => Instruction { opcode: 0x5e, addr_mode: AddrMode::ABX, operation: Operation::LSR, cycles: [7, 0] },
0x5fu8 => Instruction { opcode: 0x5f, addr_mode: AddrMode::ABX, operation: Operation::SRE, cycles: [7, 0] }, 0x5fu8 => Instruction { opcode: 0x5f, addr_mode: AddrMode::ABX, operation: Operation::SRE, cycles: [7, 0] },
// 0x60 // 0x60
@@ -233,8 +233,8 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x6eu8 => Instruction { opcode: 0x6e, addr_mode: AddrMode::ABS, operation: Operation::ROR, cycles: [6, 0] }, 0x6eu8 => Instruction { opcode: 0x6e, addr_mode: AddrMode::ABS, operation: Operation::ROR, cycles: [6, 0] },
0x6fu8 => Instruction { opcode: 0x6f, addr_mode: AddrMode::ABS, operation: Operation::RRA, cycles: [6, 0] }, 0x6fu8 => Instruction { opcode: 0x6f, addr_mode: AddrMode::ABS, operation: Operation::RRA, cycles: [6, 0] },
// 0x70 // 0x70
0x70u8 => Instruction { opcode: 0x70, addr_mode: AddrMode::REL, operation: Operation::BVS, cycles: [2, 0] }, 0x70u8 => Instruction { opcode: 0x70, addr_mode: AddrMode::REL, operation: Operation::BVS, cycles: [2, 1] },
0x71u8 => Instruction { opcode: 0x71, addr_mode: AddrMode::IZY, operation: Operation::ADC, cycles: [5, 0] }, 0x71u8 => Instruction { opcode: 0x71, addr_mode: AddrMode::IZY, operation: Operation::ADC, cycles: [5, 1] },
0x72u8 => Instruction { opcode: 0x72, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0x72u8 => Instruction { opcode: 0x72, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0x73u8 => Instruction { opcode: 0x73, addr_mode: AddrMode::IZY, operation: Operation::RRA, cycles: [8, 0] }, 0x73u8 => Instruction { opcode: 0x73, addr_mode: AddrMode::IZY, operation: Operation::RRA, cycles: [8, 0] },
0x74u8 => Instruction { opcode: 0x74, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0x74u8 => Instruction { opcode: 0x74, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
@@ -242,11 +242,11 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x76u8 => Instruction { opcode: 0x76, addr_mode: AddrMode::ZPX, operation: Operation::ROR, cycles: [6, 0] }, 0x76u8 => Instruction { opcode: 0x76, addr_mode: AddrMode::ZPX, operation: Operation::ROR, cycles: [6, 0] },
0x77u8 => Instruction { opcode: 0x77, addr_mode: AddrMode::ZPX, operation: Operation::RRA, cycles: [6, 0] }, 0x77u8 => Instruction { opcode: 0x77, addr_mode: AddrMode::ZPX, operation: Operation::RRA, cycles: [6, 0] },
0x78u8 => Instruction { opcode: 0x78, addr_mode: AddrMode::IMP, operation: Operation::SEI, cycles: [2, 0] }, 0x78u8 => Instruction { opcode: 0x78, addr_mode: AddrMode::IMP, operation: Operation::SEI, cycles: [2, 0] },
0x79u8 => Instruction { opcode: 0x79, addr_mode: AddrMode::ABY, operation: Operation::ADC, cycles: [4, 0] }, 0x79u8 => Instruction { opcode: 0x79, addr_mode: AddrMode::ABY, operation: Operation::ADC, cycles: [4, 1] },
0x7au8 => Instruction { opcode: 0x7a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0x7au8 => Instruction { opcode: 0x7a, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0x7bu8 => Instruction { opcode: 0x7b, addr_mode: AddrMode::ABY, operation: Operation::RRA, cycles: [7, 0] }, 0x7bu8 => Instruction { opcode: 0x7b, addr_mode: AddrMode::ABY, operation: Operation::RRA, cycles: [7, 0] },
0x7cu8 => Instruction { opcode: 0x7c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0x7cu8 => Instruction { opcode: 0x7c, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0x7du8 => Instruction { opcode: 0x7d, addr_mode: AddrMode::ABX, operation: Operation::ADC, cycles: [4, 0] }, 0x7du8 => Instruction { opcode: 0x7d, addr_mode: AddrMode::ABX, operation: Operation::ADC, cycles: [4, 1] },
0x7eu8 => Instruction { opcode: 0x7e, addr_mode: AddrMode::ABX, operation: Operation::ROR, cycles: [7, 0] }, 0x7eu8 => Instruction { opcode: 0x7e, addr_mode: AddrMode::ABX, operation: Operation::ROR, cycles: [7, 0] },
0x7fu8 => Instruction { opcode: 0x7f, addr_mode: AddrMode::ABX, operation: Operation::RRA, cycles: [7, 0] }, 0x7fu8 => Instruction { opcode: 0x7f, addr_mode: AddrMode::ABX, operation: Operation::RRA, cycles: [7, 0] },
// 0x80 // 0x80
@@ -267,7 +267,7 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0x8eu8 => Instruction { opcode: 0x8e, addr_mode: AddrMode::ABS, operation: Operation::STX, cycles: [4, 0] }, 0x8eu8 => Instruction { opcode: 0x8e, addr_mode: AddrMode::ABS, operation: Operation::STX, cycles: [4, 0] },
0x8fu8 => Instruction { opcode: 0x8f, addr_mode: AddrMode::ABS, operation: Operation::SAX, cycles: [4, 0] }, 0x8fu8 => Instruction { opcode: 0x8f, addr_mode: AddrMode::ABS, operation: Operation::SAX, cycles: [4, 0] },
// 0x90 // 0x90
0x90u8 => Instruction { opcode: 0x90, addr_mode: AddrMode::REL, operation: Operation::BCC, cycles: [2, 0] }, 0x90u8 => Instruction { opcode: 0x90, addr_mode: AddrMode::REL, operation: Operation::BCC, cycles: [2, 1] },
0x91u8 => Instruction { opcode: 0x91, addr_mode: AddrMode::IZY, operation: Operation::STA, cycles: [6, 0] }, 0x91u8 => Instruction { opcode: 0x91, addr_mode: AddrMode::IZY, operation: Operation::STA, cycles: [6, 0] },
0x92u8 => Instruction { opcode: 0x92, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0x92u8 => Instruction { opcode: 0x92, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0x93u8 => Instruction { opcode: 0x93, addr_mode: AddrMode::IZY, operation: Operation::AHX, cycles: [6, 0] }, 0x93u8 => Instruction { opcode: 0x93, addr_mode: AddrMode::IZY, operation: Operation::AHX, cycles: [6, 0] },
@@ -301,22 +301,22 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0xaeu8 => Instruction { opcode: 0xae, addr_mode: AddrMode::ABS, operation: Operation::LDX, cycles: [4, 0] }, 0xaeu8 => Instruction { opcode: 0xae, addr_mode: AddrMode::ABS, operation: Operation::LDX, cycles: [4, 0] },
0xafu8 => Instruction { opcode: 0xaf, addr_mode: AddrMode::ABS, operation: Operation::LAX, cycles: [4, 0] }, 0xafu8 => Instruction { opcode: 0xaf, addr_mode: AddrMode::ABS, operation: Operation::LAX, cycles: [4, 0] },
// 0xb0 // 0xb0
0xb0u8 => Instruction { opcode: 0xb0, addr_mode: AddrMode::REL, operation: Operation::BCS, cycles: [2, 0] }, 0xb0u8 => Instruction { opcode: 0xb0, addr_mode: AddrMode::REL, operation: Operation::BCS, cycles: [2, 1] },
0xb1u8 => Instruction { opcode: 0xb1, addr_mode: AddrMode::IZY, operation: Operation::LDA, cycles: [5, 0] }, 0xb1u8 => Instruction { opcode: 0xb1, addr_mode: AddrMode::IZY, operation: Operation::LDA, cycles: [5, 1] },
0xb2u8 => Instruction { opcode: 0xb2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0xb2u8 => Instruction { opcode: 0xb2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0xb3u8 => Instruction { opcode: 0xb3, addr_mode: AddrMode::IZY, operation: Operation::LAX, cycles: [5, 0] }, 0xb3u8 => Instruction { opcode: 0xb3, addr_mode: AddrMode::IZY, operation: Operation::LAX, cycles: [5, 1] },
0xb4u8 => Instruction { opcode: 0xb4, addr_mode: AddrMode::ZPX, operation: Operation::LDY, cycles: [4, 0] }, 0xb4u8 => Instruction { opcode: 0xb4, addr_mode: AddrMode::ZPX, operation: Operation::LDY, cycles: [4, 0] },
0xb5u8 => Instruction { opcode: 0xb5, addr_mode: AddrMode::ZPX, operation: Operation::LDA, cycles: [4, 0] }, 0xb5u8 => Instruction { opcode: 0xb5, addr_mode: AddrMode::ZPX, operation: Operation::LDA, cycles: [4, 0] },
0xb6u8 => Instruction { opcode: 0xb6, addr_mode: AddrMode::ZPY, operation: Operation::LDX, cycles: [4, 0] }, 0xb6u8 => Instruction { opcode: 0xb6, addr_mode: AddrMode::ZPY, operation: Operation::LDX, cycles: [4, 0] },
0xb7u8 => Instruction { opcode: 0xb7, addr_mode: AddrMode::ZPY, operation: Operation::LAX, cycles: [4, 0] }, 0xb7u8 => Instruction { opcode: 0xb7, addr_mode: AddrMode::ZPY, operation: Operation::LAX, cycles: [4, 0] },
0xb8u8 => Instruction { opcode: 0xb8, addr_mode: AddrMode::IMP, operation: Operation::CLV, cycles: [2, 0] }, 0xb8u8 => Instruction { opcode: 0xb8, addr_mode: AddrMode::IMP, operation: Operation::CLV, cycles: [2, 0] },
0xb9u8 => Instruction { opcode: 0xb9, addr_mode: AddrMode::ABY, operation: Operation::LDA, cycles: [4, 0] }, 0xb9u8 => Instruction { opcode: 0xb9, addr_mode: AddrMode::ABY, operation: Operation::LDA, cycles: [4, 1] },
0xbau8 => Instruction { opcode: 0xba, addr_mode: AddrMode::IMP, operation: Operation::TSX, cycles: [2, 0] }, 0xbau8 => Instruction { opcode: 0xba, addr_mode: AddrMode::IMP, operation: Operation::TSX, cycles: [2, 0] },
0xbbu8 => Instruction { opcode: 0xbb, addr_mode: AddrMode::ABY, operation: Operation::LAS, cycles: [4, 0] }, 0xbbu8 => Instruction { opcode: 0xbb, addr_mode: AddrMode::ABY, operation: Operation::LAS, cycles: [4, 1] },
0xbcu8 => Instruction { opcode: 0xbc, addr_mode: AddrMode::ABX, operation: Operation::LDY, cycles: [4, 0] }, 0xbcu8 => Instruction { opcode: 0xbc, addr_mode: AddrMode::ABX, operation: Operation::LDY, cycles: [4, 1] },
0xbdu8 => Instruction { opcode: 0xbd, addr_mode: AddrMode::ABX, operation: Operation::LDA, cycles: [4, 0] }, 0xbdu8 => Instruction { opcode: 0xbd, addr_mode: AddrMode::ABX, operation: Operation::LDA, cycles: [4, 1] },
0xbeu8 => Instruction { opcode: 0xbe, addr_mode: AddrMode::ABY, operation: Operation::LDX, cycles: [4, 0] }, 0xbeu8 => Instruction { opcode: 0xbe, addr_mode: AddrMode::ABY, operation: Operation::LDX, cycles: [4, 1] },
0xbfu8 => Instruction { opcode: 0xbf, addr_mode: AddrMode::ABY, operation: Operation::LAX, cycles: [4, 0] }, 0xbfu8 => Instruction { opcode: 0xbf, addr_mode: AddrMode::ABY, operation: Operation::LAX, cycles: [4, 1] },
// 0xc0 // 0xc0
0xc0u8 => Instruction { opcode: 0xc0, addr_mode: AddrMode::IMM, operation: Operation::CPY, cycles: [2, 0] }, 0xc0u8 => Instruction { opcode: 0xc0, addr_mode: AddrMode::IMM, operation: Operation::CPY, cycles: [2, 0] },
0xc1u8 => Instruction { opcode: 0xc1, addr_mode: AddrMode::IZX, operation: Operation::CMP, cycles: [6, 0] }, 0xc1u8 => Instruction { opcode: 0xc1, addr_mode: AddrMode::IZX, operation: Operation::CMP, cycles: [6, 0] },
@@ -335,20 +335,20 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0xceu8 => Instruction { opcode: 0xce, addr_mode: AddrMode::ABS, operation: Operation::DEC, cycles: [6, 0] }, 0xceu8 => Instruction { opcode: 0xce, addr_mode: AddrMode::ABS, operation: Operation::DEC, cycles: [6, 0] },
0xcfu8 => Instruction { opcode: 0xcf, addr_mode: AddrMode::ABS, operation: Operation::DCP, cycles: [7, 0] }, 0xcfu8 => Instruction { opcode: 0xcf, addr_mode: AddrMode::ABS, operation: Operation::DCP, cycles: [7, 0] },
// 0xd0 // 0xd0
0xd0u8 => Instruction { opcode: 0xd0, addr_mode: AddrMode::REL, operation: Operation::BNE, cycles: [2, 0] }, 0xd0u8 => Instruction { opcode: 0xd0, addr_mode: AddrMode::REL, operation: Operation::BNE, cycles: [2, 1] },
0xd1u8 => Instruction { opcode: 0xd1, addr_mode: AddrMode::IZY, operation: Operation::CMP, cycles: [5, 0] }, 0xd1u8 => Instruction { opcode: 0xd1, addr_mode: AddrMode::IZY, operation: Operation::CMP, cycles: [5, 1] },
0xd2u8 => Instruction { opcode: 0xd2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0xd2u8 => Instruction { opcode: 0xd2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0xd3u8 => Instruction { opcode: 0xd3, addr_mode: AddrMode::IZY, operation: Operation::DCP, cycles: [7, 0] }, 0xd3u8 => Instruction { opcode: 0xd3, addr_mode: AddrMode::IZY, operation: Operation::DCP, cycles: [7, 0] },
0xd4u8 => Instruction { opcode: 0xd4, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0xd4u8 => Instruction { opcode: 0xd4, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
0xd5u8 => Instruction { opcode: 0xd5, addr_mode: AddrMode::ZPX, operation: Operation::CMP, cycles: [4, 0] }, 0xd5u8 => Instruction { opcode: 0xd5, addr_mode: AddrMode::ZPX, operation: Operation::CMP, cycles: [4, 0] },
0xd6u8 => Instruction { opcode: 0xd6, addr_mode: AddrMode::ZPX, operation: Operation::DEC, cycles: [6, 0] }, 0xd6u8 => Instruction { opcode: 0xd6, addr_mode: AddrMode::ZPX, operation: Operation::DEC, cycles: [6, 0] },
0xd7u8 => Instruction { opcode: 0xd7, addr_mode: AddrMode::ZPX, operation: Operation::DCP, cycles: [7, 0] }, 0xd7u8 => Instruction { opcode: 0xd7, addr_mode: AddrMode::ZPX, operation: Operation::DCP, cycles: [7, 1] },
0xd8u8 => Instruction { opcode: 0xd8, addr_mode: AddrMode::IMP, operation: Operation::CLD, cycles: [2, 0] }, 0xd8u8 => Instruction { opcode: 0xd8, addr_mode: AddrMode::IMP, operation: Operation::CLD, cycles: [2, 0] },
0xd9u8 => Instruction { opcode: 0xd9, addr_mode: AddrMode::ABY, operation: Operation::CMP, cycles: [4, 0] }, 0xd9u8 => Instruction { opcode: 0xd9, addr_mode: AddrMode::ABY, operation: Operation::CMP, cycles: [4, 0] },
0xdau8 => Instruction { opcode: 0xda, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0xdau8 => Instruction { opcode: 0xda, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0xdbu8 => Instruction { opcode: 0xdb, addr_mode: AddrMode::ABY, operation: Operation::DCP, cycles: [7, 0] }, 0xdbu8 => Instruction { opcode: 0xdb, addr_mode: AddrMode::ABY, operation: Operation::DCP, cycles: [7, 0] },
0xdcu8 => Instruction { opcode: 0xdc, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0xdcu8 => Instruction { opcode: 0xdc, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0xddu8 => Instruction { opcode: 0xdd, addr_mode: AddrMode::ABX, operation: Operation::CMP, cycles: [4, 0] }, 0xddu8 => Instruction { opcode: 0xdd, addr_mode: AddrMode::ABX, operation: Operation::CMP, cycles: [4, 1] },
0xdeu8 => Instruction { opcode: 0xde, addr_mode: AddrMode::ABX, operation: Operation::DEC, cycles: [7, 0] }, 0xdeu8 => Instruction { opcode: 0xde, addr_mode: AddrMode::ABX, operation: Operation::DEC, cycles: [7, 0] },
0xdfu8 => Instruction { opcode: 0xdf, addr_mode: AddrMode::ABX, operation: Operation::DCP, cycles: [7, 0] }, 0xdfu8 => Instruction { opcode: 0xdf, addr_mode: AddrMode::ABX, operation: Operation::DCP, cycles: [7, 0] },
// 0xe0 // 0xe0
@@ -369,8 +369,8 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0xeeu8 => Instruction { opcode: 0xee, addr_mode: AddrMode::ABS, operation: Operation::INC, cycles: [6, 0] }, 0xeeu8 => Instruction { opcode: 0xee, addr_mode: AddrMode::ABS, operation: Operation::INC, cycles: [6, 0] },
0xefu8 => Instruction { opcode: 0xef, addr_mode: AddrMode::ABS, operation: Operation::ISB, cycles: [7, 0] }, 0xefu8 => Instruction { opcode: 0xef, addr_mode: AddrMode::ABS, operation: Operation::ISB, cycles: [7, 0] },
// 0xf0 // 0xf0
0xf0u8 => Instruction { opcode: 0xf0, addr_mode: AddrMode::REL, operation: Operation::BEQ, cycles: [2, 0] }, 0xf0u8 => Instruction { opcode: 0xf0, addr_mode: AddrMode::REL, operation: Operation::BEQ, cycles: [2, 1] },
0xf1u8 => Instruction { opcode: 0xf1, addr_mode: AddrMode::IZY, operation: Operation::SBC, cycles: [5, 0] }, 0xf1u8 => Instruction { opcode: 0xf1, addr_mode: AddrMode::IZY, operation: Operation::SBC, cycles: [5, 1] },
0xf2u8 => Instruction { opcode: 0xf2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] }, 0xf2u8 => Instruction { opcode: 0xf2, addr_mode: AddrMode::IMP, operation: Operation::KIL, cycles: [1, 0] },
0xf3u8 => Instruction { opcode: 0xf3, addr_mode: AddrMode::IZY, operation: Operation::ISB, cycles: [7, 0] }, 0xf3u8 => Instruction { opcode: 0xf3, addr_mode: AddrMode::IZY, operation: Operation::ISB, cycles: [7, 0] },
0xf4u8 => Instruction { opcode: 0xf4, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] }, 0xf4u8 => Instruction { opcode: 0xf4, addr_mode: AddrMode::ZPX, operation: Operation::NOP, cycles: [4, 0] },
@@ -378,11 +378,11 @@ static INSTRUCTION_SET: Map<u8, Instruction> = phf_map! {
0xf6u8 => Instruction { opcode: 0xf6, addr_mode: AddrMode::ZPX, operation: Operation::INC, cycles: [6, 0] }, 0xf6u8 => Instruction { opcode: 0xf6, addr_mode: AddrMode::ZPX, operation: Operation::INC, cycles: [6, 0] },
0xf7u8 => Instruction { opcode: 0xf7, addr_mode: AddrMode::ZPX, operation: Operation::ISB, cycles: [7, 0] }, 0xf7u8 => Instruction { opcode: 0xf7, addr_mode: AddrMode::ZPX, operation: Operation::ISB, cycles: [7, 0] },
0xf8u8 => Instruction { opcode: 0xf8, addr_mode: AddrMode::IMP, operation: Operation::SED, cycles: [2, 0] }, 0xf8u8 => Instruction { opcode: 0xf8, addr_mode: AddrMode::IMP, operation: Operation::SED, cycles: [2, 0] },
0xf9u8 => Instruction { opcode: 0xf9, addr_mode: AddrMode::ABY, operation: Operation::SBC, cycles: [4, 0] }, 0xf9u8 => Instruction { opcode: 0xf9, addr_mode: AddrMode::ABY, operation: Operation::SBC, cycles: [4, 1] },
0xfau8 => Instruction { opcode: 0xfa, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] }, 0xfau8 => Instruction { opcode: 0xfa, addr_mode: AddrMode::IMP, operation: Operation::NOP, cycles: [2, 0] },
0xfbu8 => Instruction { opcode: 0xfb, addr_mode: AddrMode::ABY, operation: Operation::ISB, cycles: [7, 0] }, 0xfbu8 => Instruction { opcode: 0xfb, addr_mode: AddrMode::ABY, operation: Operation::ISB, cycles: [7, 0] },
0xfcu8 => Instruction { opcode: 0xfc, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 0] }, 0xfcu8 => Instruction { opcode: 0xfc, addr_mode: AddrMode::ABX, operation: Operation::NOP, cycles: [4, 1] },
0xfdu8 => Instruction { opcode: 0xfd, addr_mode: AddrMode::ABX, operation: Operation::SBC, cycles: [4, 0] }, 0xfdu8 => Instruction { opcode: 0xfd, addr_mode: AddrMode::ABX, operation: Operation::SBC, cycles: [4, 1] },
0xfeu8 => Instruction { opcode: 0xfe, addr_mode: AddrMode::ABX, operation: Operation::INC, cycles: [7, 0] }, 0xfeu8 => Instruction { opcode: 0xfe, addr_mode: AddrMode::ABX, operation: Operation::INC, cycles: [7, 0] },
0xffu8 => Instruction { opcode: 0xff, addr_mode: AddrMode::ABX, operation: Operation::ISB, cycles: [7, 0] }, 0xffu8 => Instruction { opcode: 0xff, addr_mode: AddrMode::ABX, operation: Operation::ISB, cycles: [7, 0] },
}; };